A power module supplying a large current needs a solution to a heat generated by supplying the large current. One solution to the heat generation problem is how efficiently the generated heat is dissipated to the outside, wherefore various techniques for external dissipation have been invented and adopted to the power module.
Further, another solution needed to be considered is a difference in the linear expansion coefficient among components in the power module. For example, electronic parts such as elements, ICs, and capacitors, and a substrate in the power module are electrically connected to one another by soldering in an appropriate manner. However, there is known a phenomenon that a difference in the linear expansion coefficient between an electronic component and the substrate causes a crack at a soldered portion due to a cyclic fatigue, which eventually results in a breakage of the components.
As a method for retarding the breakage phenomenon, there is known a technique disclosed by Patent Literature 1 that applies and coats an epoxy resin having a linear expansion coefficient similar to a linear expansion coefficient of a solder to electronic components to suppress a stress concentration to an origin of a solder crack and thereby extend the service life of the soldered portion. Further, Patent Literature 1 proposes a structure for improving the service life of a soldered portion by filling an entire substrate disposed in a module with an epoxy resin having a linear expansion coefficient similar to a linear expansion coefficient of the solder.
Further, there is known a structure disclosed by Patent Literature in which the circumference of a wire is coated with a soft polyimide-based resin, and semiconductor elements are potted with an epoxy resin having a linear expansion coefficient similar to a linear expansion coefficient of the solder to prevent a binding force of the epoxy resin from being applied to the wire.
Further, as a method for partitioning a region on a substrate, there is known a method that encloses semiconductor elements with a frame as a separate component, as disclosed in Patent Literature 3.